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Processor register
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#	Item
41	T9000 - superscalar transputer Richard Forsyth Bob Krysiak Roger Shepherd INrvl0S Limited - SGS-Thomson Microelectronics Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:50 Central processing unit Stack machines Microprocessors Parallel computing Transputer Computer architecture Processor register CPU cache IDL Instruction set
42	System V Application Binary Interface x86-64TM Architecture Processor Supplement Draft Version 0.21 Edited by Jan Hubicka , Andreas Jaeger2 , Mark Mitchell3 1 Add to Reading List Source URL: refspecs.linuxbase.org Language: English - Date: 2015-01-28 11:44:48 X86 architecture X86-64 Application binary interface Calling convention X86 64-bit computing P5 X87 Intel 80386 Intel Processor register X32 ABI
43	Advanced Parallel Architecture Annalisa Massini Vector architecture 2 Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-04-28 17:33:30 Central processing unit Parallel computing Computer architecture Supercomputers Instruction set architectures Processor register Cray-1 MIPS instruction set SIMD Instruction set 64-bit computing Euclidean vector
44	Lecture 4: Modeling Sparse Matrix-Vector Multiply William Gropp www.cs.illinois.edu/~wgropp Sustained Memory Bandwidth Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2015-01-15 10:20:20 Central processing unit Computer memory Cache Programming languages CPU cache Sparse matrix Processor register Fortran Data
45	Virtual Machine Showdown: Stack Versus Registers Yunhe Shi, David Gregg, Andrew Beatty M. Anton Ertl Department of Computer Science Add to Reading List Source URL: www.usenix.org Language: English - Date: 2005-08-02 11:12:30 Central processing unit Assembly languages Java virtual machine Android Programming language implementation Stack machine Java bytecode Dalvik Instruction set Processor register Stack Opcode
46	Stratified Synthesis: Automatically Learning the x86-64 Instruction Set Stefan Heule Eric Schkufza Add to Reading List Source URL: raw.githubusercontent.com Language: English Instruction set architectures Central processing unit X86 instructions X86 architecture Computer architecture X86 Instruction set Processor register ARM architecture Low-level programming language NOP Intel
47	Runtime Register Allocation Kemal Ebcio˘glu and Vivek Sarkar IBM T.J. Watson Research Center P.O. Box 704 Yorktown Heights, NY 10598, USA {kemal,vsarkar}@us.ibm.com Add to Reading List Source URL: akkartik.name Language: English - Date: 2006-03-07 01:56:23 Central processing unit Computer architecture NCR Corporation Processor register CPU cache
48	From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware Haibo Chen† , Xi Wu† , Liwei Yuan† , Binyu Zang† , Pen-chung Yew‡ , and Frederic T. Chong§ † ‡ Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-01-05 23:25:08 Computer architecture Computing Computer engineering Central processing unit Instruction set architectures Processor register Itanium X86 CPU cache Optimizing compiler 64-bit computing Pointer
49	Advanced x86: BIOS and System Management Mode Internals SMRAM (System Management RAM) Xeno Kovah && Corey Kallenberg LegbaCore, LLC Add to Reading List Source URL: opensecuritytraining.info Language: English - Date: 2015-10-14 22:08:48 Computer architecture Computing Computer engineering X86 architecture Rootkits System Management Mode IBM PC compatibles Central processing unit X86-64 X86 SMI Processor register
50	Procedure Call Standard for the ARM Architecture Add to Reading List Source URL: infocenter.arm.com Language: English Subroutines Central processing unit Acorn Computers ARM architecture Calling convention Application binary interface Pointer 64-bit computing Processor register Stack SIMD Instruction set